A bandwidth-regulating architecture in the interconnection system of a SoC

Abstract

Nowadays, inside a chip, it is possible to integrate a considerable number of Processing Elements (PE) that collaborate for the execution of a task. Several studies have shown that currently the performance of a System-on-Chip (SoC) depends more on the interconnection system that links them than on their individual processing capacity. In order for the PE's as a whole to execute the assigned task while meeting Quality of Service (QoS) requirements such as latency and throughput, they need to be allowed access to shared resources with varying regularity. In this paper we show the hardware architecture of a bandwidth regulator that allows to differentially allocate the time of use of the interconnection system, in this case a bus-based interconnection system, by modifying at run-time the support weights of a Weighted Round-Robin Arbiter.